Datacube History and Products from 1979 to 2005

The Worlds Top Performance Image Processing Hardware

By Dave Erickson

Datacube Youtube Video

mv20

Intro

I was with Datacube for 17 years from 1981 to 1997. First as a consulting engineer, then full time as a senior EE. I was soon Director of Engineering. Datacube was the leading high-performance image processing company in the world. Our products performed real-time (frame-rate) image processing with billions of operations per second at a time when the fastest commercial CPUs were 10-100 MIPS.  We developed 5 generations of imaging products, consisting of mostly board-level image processors and modules. We sold to the industrial, medical, military, scientific and entertainment markets. We had a great team of Hardware, Software, and Application engineers and had a blast doing it.

Company co-founder, J Dunn, developed many high performance Multibus boards including the first frame grabber, the VG120, 6 bit digitizer and display. J was an early leader using programmable logic PALs to increase logic density. In 1980 Datacube developed the first board-level video frame grabbers for the standard busses at the time: Multibus, DEC Q-Bus, then VME and PC/AT. Here are the VG120 circa 1980 and the QVG123 circa 1982, early frame grabbers.
vg120  qvg123
Here is an even earlier Datacube Multibus EPROM board, CM116.
cm116

By 1983, other frame-grabber companies were adding real-time, single point, signal processing to their frame grabbers. We needed to compete, and had a decent way to synchronize multiple frame grabbers, and so developed a single point multiply-accumulator. It could perform 3x3 FIR filtering in 9 frame times. It used pipelined processing where every operation was performed in parallel. The basic data was a full 2D frame of video data. Processing was (mostly) performed in a raster: Left to right, top to bottom.

The major advantages of pipelined processing are two-fold. First is that all processing elements operate in parallel. No device is waiting for another to perform its processing. The second is that each processing element is designed to perform a specific function, so it's memory and gate count are very efficient. Adders and multipliers are small and efficient, and are operating near 100% of the time. Compared to a CPU where every operation is performed serially, very high performance can be achieved.

Here is a video introduction to Datacube products video from 1999. It is a good intro to pipelined processing, the Datacube products, and services. It's 10+ minutes, and low res, but pretty technical for a marketing video. Datacube Product Presentation Video
 
video

MaxVideo 10

By the mid 80's, VME was the platform of choice for industrial and military control systems, and was beginning to take off for medical and imaging applications. At that time, General Motors made a simple rule for their industrial automation that affected the industry: Though Shalt Use VME. It was a wise choice since VME bus is a great standard. It is mechanically and electrically robust and offered high performance. Major companies like Sun, Motorola, and Force, and many mid-size and small companies fully embraced VME. The US military had embraced COTS (commercial off-the-shelf) and preferred VME for the same reasons.

A few of us engineers and marketing people at Datacube did a customer road-trip where we queried our existing and potential new customers for what they were looking for in Imaging Hardware. They pretty much universally said:
 We went to work specifying and designing the first 7 VME boards and called it MAXVideo. MAX Video stands for Modular Architecture for eXpandable Video.  Based on the ECL clock synchronization method that we used on our previous 123 family frame grabbers, we developed a standard bus for routing 8 bit digital video between boards. Called MaxBus, of course. Here are the first 7 MaxVideo boards.
We demo-ed the first commercial 3x3 real-time image filter in the world, at the Machine Vision trade show in Detroit, about 1985.  The demo used a Digimax and VFIR to do a 3x3 edge filter on real-time video. It rotated the edge direction of the filter every few frames by changing the 9 filter coefficients.  Customers were blown away. We signed up 10 customers for the 7 board set in various industrial, automotive, medical, and military markets.  We went to work finishing the boards and hand-soldering 10 of each board. Most of the boards were shippable at Rev 0, with some minor reworks.

In terms of technology, these boards used thru-hole technology, mostly DIPs. we made extensive use of early programmable logic, mostly bipolar PALs, and 74F and 74LS logic. Schematics were hand-drawn, and the 4-6 layer PC boards were almost all hand-taped. Our PCB contractor had two excellent PCB designers who were masters at hand-taped layout. People would admire our boards and wonder which CAD tool was used. The board layouts were that neat and clean.  Ironically, only Digimax was laid out with CAD, and it was the last PCB to be built, literally months late as the PCB designer struggled to learn his new CAD software. Despite the fact that every test system needed a Digimax, since it was the only MaxBus master that provided the ECL timing, we only had one wire-wrapped Digimax that we shared. Here it is below. Our Technician, Ephrem Parada hand wire-wrapped this board. It took one very full week, the man was an artist.

digimax ww  digimax ww

digimax

Here are some of the other original seven MaxVideo boards. Thanks to Artisan Technology for the images. Artisan sells Datacube boards. Framestore-10 designed by J Dunn and I. VFIR and SNAP and Featuremax were designed by Shep Siegel. MaxSP was designed by Rich DiSilvestro and Shep. I designed Digimax and Protomax. The labeled ICs are programmable devices, mostly bipolar PALs. We designed over 1200 different programmable devices in the 25 years Datacube was in business.
Shown are Framestore, Featuremax and MaxSP.
framefeaturemax
maxsp



Shortly after the success of the first 7 MaxVideo boards, We hired another awesome Hardware Engineer, John Bloomfield. John had worked at Ampex with Shep on ADO (Ampex Digital Optics). John was instrumental in developing ROI (Region of Interest) processing including ROIStore, MaxScan, VFIRMkII, AU800 ASIC, 2 generations of high-res graphics,  and many other products.

In the next few years we added new MaxVideo boards at a rapid pace. Because the architecture supported arbitrary pipeline processing, We could design new processing modules quickly and efficiently as our engineers conceived of them, as the new technology allowed them, or as customers requested them.  New technologies included CPLDs, FPGAs, custom ASICs and off-the-shelf signal processing ICs from Analog Devices, LSI Logic, and others. Here are ROIStore and VFIRMkII in all their late 80's glory.

roistoreVFIRMkII

Shep developed our first generation of Image Warpers, able to zoom, rotate, translate and do perspective transform image warping in real time. This was a 3-6 board set with two each Addgen Address generators, Interp interpolators, and XFS Transposing frame stores. Military contractors, particularly Lockheed-Martin and IBM Gaithersburg were particularly interest in our warping and ROI processing to do image roaming on huge satellite images.

We built the MaxView board-set to support high resolution display and large image exploitation applications
    Graphics up to 1280 x 1024, with live imaging in a window.
    MegaStore 8MB image storage
    Second generation Warper in a 2 board set: Addgen MKII and Interp MKII

Technologies Used

All VME boards used 5V logic, PALS, FPGAs and ASICS. For MaxPCI we moved nearly all logic to 3.3V logic.

PALs
    Bipolar MMI
    CMOS GALs
    22V10s
   
CPLDs
    Altera 1st gen EP600/900
    Altera 5000 and 7000 series, 32 to 128 cells
    MAXII
   
FPGAs
    Xilinx 2000, the first FPGAs
    Xilinx 3000 and 4000
    Actel 1000 series
   
Custom ASICs
    MaxMux Crosspoint
    AU800 for MV20/200/250
    AU-40 for MaxPCI
    VSIM Image Memory
    IXP Crosspoint for MaxPCI

Memory
    Nearly every type of SRAM, DRAM, VRAM, SDRAM, Multiport SRAM and FIFOs

Off-the-shelf ASICs
    LSI Logic L64240 64 point 8x8 convolver
    LSI Logic L64250 Histogram / Hough Transform
    LSI Logic L64270 Digital Crosspoint Switch
    Waferscale WSI PAC1000-12 Programmable Peripheral Interface

DSP Hardware
    ADI ADSP1008 8x8 multiplier
    ADI ADSP1010 Integer AU
    ADI ADSP2100 16b integer DSP
    TI FPU

Graphics Processors
    Hitachi HD6840
    TI 34020

ASICs

We developed several image processing ASICs. My first (and only) custom ASIC design was a crosspoint matrix switch. It was a 2 micron device, with about 2000 gates in an 84 pin PLCC package. It was a non-blocking crosspoint, meaning that it could arbitrarily connect any input data path to any number of outputs. Our MaxMux VME board used 2 of these ASICs, and allowed customers to build re-configurable pipelines. Subsequently, LSI logic built a large crosspoint chip: 64x64, that we used four of in our flagship VME processors: MaxVideo MV20, 200 and 250.  For the 40Mhz MaxPCI product we designed a giant crosspoint ASIC: IXP. MaxPCI used 5 of these beasts to connect every processing element on the board (and on adjacent boards) to each other.  After my initial crosspoint design, our ASICs became exponentially more complex, and were designed by real ASIC designers.
Here is the MaxMux board, containing two MaxMux ASICs.

maxmux

AU (Arithmetic Unit) ASIC was a general purpose arithmetic unit with Linear, Non-linear and Statistical processing. Designed by John Bloomfield, Shep, and Steve Gabriel, it has four 11 bit multipliers, seven ALUs, two run-length encoders, and two statistics processors. AU  was a real problem solver and customers greatly appreciated it's capabilities.

MV20 used a 1MB memory module, in the form-factor of a Memory SIMM, but with a triple-ported image memory. It could simultaneously acquire and output a ROI, while also being accessible from a CPU across the VME bus. It used 14 ICs consisting of programmable logic devices and VRAM (video DRAM) memories.  We wanted larger memories, lower cost and power, some more flexible features, Here is the VSIM specification. Shep Siegel designed the D52 ASIC: VSIM, to address these needs. Here are the requirements for the VSIM ASIC.
 Shep developed 3 generations of Image Warpers. The first used 6 VME boards, the second 2 boards. A fair amount of board real estate, power and cost. We decided that if Image Warping was going to succeed commercially, we needed to reduce the board area, power and cost significantly. It needed an ASIC. Shep designed the MiniWarper MW4242 ASIC which was packaged on a MaxModule that could be plugged onto MV20/200/250.

Here is MiniWarper ASIC Specification

MaxPCI

maxpci
In 1996, things were about to change. Up to then, MaxVideo was entirely VME based. VME, Sun-OS and Solaris, OS-9, and Lynx-OS has served our markets well, but Windows 95 and Pentium PCs with PCI bus were coming on strong. A PC version of MaxVideo was required. MaxPCI was developed over 2 years. VSIM was already capable of MAX PCI's target processing speed of 40 MHz, but everything else needed to be updated or redesigned. The core of MaxPCI was a new, giant crosspoint ASIC: 50 x 40 x 8 with full ROI timing crosspoint and many imaging functions as well, developed by Erich. John redesigned the AU ASIC to operate at 40 MHz and repackaged it in a amaller, lower cost TQFP. A new statistics unit was developed. Tim Ganley developed the MaxAcq acquisition subsystem and Dave developed the first of a new family of 40 MHz analog and digital front-ends, QA and QD. A new family of processing modules, PSMODs  was developed by Paul Secinaro. MaxPCI featured:
 For an integrated display, a VGA board from another graphics board company, Univision was used. For a real-time disc solution. Shep developed ND, a software solution for real-time disc access.

Meanwhile Datacube recognized the need to better help its customers develop complex solutions in the medical, web inspection and machine vision markets. So three vertical integration development groups were formed. Shep headed Medical, Dave Simmons headed Web, and Scott Roth headed Machine vision. Each of these groups developed systems for OEMs in their respective markets: Bobst and Crane Paper in web, Picker in Medical, and several companies in Machine Vision.

MaxVideo Teardown

I recently purchased some of the technology that we developed back then. In the 5-6 generations of image processing we developed, it was about in the middle of that range, so it pretty typical of late-80s technology. The purchase consisted of a 20 slot VME MaxBox, containing two MaxScan digitizers and a MV20 Image Processor. The CPU was a Sun Sparc with Video board and ....

I thought it would be interesting to do a tear-down to get a snapshot of the leading edge technology at that time. To literally blow the dust off of some amazing old technology and see what I can remember about products that I designed 25-35 years ago and for which I have literally no information. No schematics, not even a data sheet. I'll need to reverse-engineer it from memory and from looking at old PC boards.

Here is the system as it was shipped. I removed a large collection of wide ribbon cables that were used to connect external hard drives and image sensors.
 
maxbox

The first 4 slots contain a Sun Sparc-4 CPU, graphics board, and 2 memory boards. It will be interesting to see if the Sun Sparc is alive.

The next is a single empty slot. Next is a MaxVideo MV20, which uses 2 slots. It is fully configured with AS, AG, 6 ROI Memories and an AP processor board containing an 8x8 convolver, Look-up-table (LUT) and Histogram / Hough processor.

Then there are two MaxScan boards, cabled to the MV20.

The next slot is a MaxBus to SCSI Hard Drive controller made by Storage Concepts (SC), a third-party MaxVideo supplier. It too was cabled to the MV20

Next is another SCSI hard drive controller, also by SC. The last is an unknown board. It looks like it has no VME interface, it looks like just some kind of interface board. .

So the system contained 2 Acquisition boards  labeled "VIS, IR1 and IR2". It has a rare Storage Concepts MaxBus to SCSI Raid Disk controller and a powerful MV20 image processor. So apparently the system was used to collect multi-spectral sensor data, process it, and store it to hard drive. Then perhaps the image data was processed by the Sparc4 and sent elsewhere. There are no other clues as to its intended use.

I turned it on and sure enough the fans and CPU LEDs came alive. Power was OK. The box consumed about 30 Watts from the AC line. That's about right. I took out each board and they were fairly clean, as was the front air filter, especially considering their 30+ year age. The boards needed a light dusting only.


Should I revive it?

I'm sure this video will result in people asking if the system I have can be restored. It may be possible, but this would require a heap of work, all the while hoping that some irreplaceable hardware is working. All with no manuals, schematics... A lot of work for little payback.
  1. Test / debug / repair or replace 1990 Sun Sparc-4 CPU
  2. Find and install an appropriate version of Datacube ImageFlow software
  3. Write a demo / test application in ImageFLow
MaxScan adds more complications. Without a manual I can't easily figure out how to configure its many jumpers and trimpots.

Reviving the VME Sun Sparc4  is its own project. I'll keep at it until it gets too hard or expensive.

MaxVideo 20: MV20

By the late 80's we had developed about 15 MaxVideo VME boards. The technology had advanced to where we could significantly shrink many functions. SMT was widely available. PC Memory came in SIMM packages, and we could make a triple-ported image memory that small. MaxScan Universal cameras interface could be implemented in 2 different modules, one for analog sensors and one for digital sensors. For Display, VGA had become the standard. We wanted to implement the digitizer and a display module in a  plug-in SIMM package similar to the Image Memories. LSI Logic offered several ASICs for pipelined imaging, including a large crosspoint. Imaging modules could be implemented in sizes much smaller than the full 6U VME size. In addition, the native pipelined data speed could be increased from the original 10MHz to 20MHz. Several of the previous MaxVideo boards already had 20MHz capability.
mv20

For IC packaging,  the early boards all used through-hole DIPs. We used SMT on early 90's and later boards. Early socketed PLCC packages made way for QFPs and PGAs. MV20 was conceived, designed, and built. In two VME slots, it would contain the following imaging functions which were equivalent of up to  about 10 VME boards. Despite its small size, we still wanted it to be modular and expandable, allowing flexibility on small plug-in modules. A large crosspoint provided the full interconnect flexibility that MaxBus cables had, but with full programmability.

Here is the block diagram of MV20/200. The big crosspoint is shown as a large "U". It allows any output to drive any one or more inputs.

mv20

HiRes view of MV20.

mv20

And without the AP so you can see all the motherboard components.

mv20noAP

And the back side. 10 Layer board, I believe.

mv20rear

Several new 1990 technologies were used on MV20:

MaxBox

The first MaxVideo systems used anywhere from 2 to 18 or more VME boards, plus a CPU and whatever other peripherals the customer needed. Datacube boards drew about  3-5 amps of +5V per board. The challenge of off-the-shelf enclosures for VME was that they needed heavy power supplies, high current backplanes, and good cooling. At the time, such enclosures were big, heavy and expensive. We were building large systems in-house, and wanted our customers to be able to do the same. We bought several 7-12 slot VME backplanes for development and production test, and liked Hybricon best. Some other backplanes used cheap Molex KK-156 power connectors, and we saw a few burned power connectors on a few backplanes. Most of the large 20 slot VME boxes had the boards facing front, but with no cover for EMI, etc. They assumed that all cables would be routed to the front which was OK for a lab, but not for a deployed system.  We needed to spare our customers from the same struggles that we went through. Hybricon's backplanes were very well made and used heavy screw terminals for the +5V power supply pins. MaxBox requirements:
 We wanted custom rear panel cutouts for custom connectors. Again, something that no off-the-shelf enclosure provided. I chose the card cage, backplane, power supply,  fans, standard cabling, and the rear panel. To accommodate future, unknown connectors, I made a rectangular cutout that could be easily customized for connectors. I sketched out the idea and handed it to our Mechanical Engineer consultant. We had no ME on staff. He came back with what was very close to the final MaxBox. It had a nice looking molded, vented front panel. Cooling fans were in the middle of the box to minimize fan noise. We built up a few initial units and were very happy with the results. 

We sold several hundred MaxBoxes, but the biggest business came from a derived product. Martin-Lockheed built "Lantirn",  an advanced FLIR and Radar avionics targeting pod designed to mount below a fighter jet. The system was used extensively in the first Gulf war. Datacube hardware was not used in the Lantirn avionics package. Lantirn required a test and calibration system for each air base that deployed it. Martin Lockheed used Datacube boards in a MaxBox to to provide the Image processing in the Lantirn test Lantirn systems. Martin approached Datacube to build an ruggedized VME system and enclosure for the Lantirn Test system. They liked MaxBox, and required a ruggedized and mil-spec version of it. We shipped dozens of these systems over several years.

As our boards became more dense, 20 VME slots was overkill. So we developed 12 and 5 slot chassis as well.

MaxScan

The second tier of MaxVideo boards had ROI (Region of Interest) processing. This allowed larger images or smaller images with faster frame rates, in arbitrary sizes to be processed. We needed a flexible, camera sensor acquisition board to be able to handle any type of sensors such as large area, high frame rate, and line-scan sensors, as well as digital output sensors. MaxScan was conceived and born.
John Bloomfield and I designed this board. John was the inventor of ROI technology, I was the analog and sensor guy. We pored over the available line scan and area scan sensor specs  from EG&G Reticon, Dalsa, Sony, Panasonic, Fairchild, and others, making sure to accommodate each one's unique interface requirements. We accommodated the new TDI  (Time Delay Integration) line-scan cameras at the time. Our Web Inspection group was key in providing their sensor requirements. The board used the new Xilinx FPGAs, their very first devices. The XC2064 and XC2100 had 64 and 100 cells, respectively. Here is a detailed block diagram of MaxScan.

maxscan

Here is a MaxScan board. Left side is the analog section, then the two 24 PIN wide DIP FIFOs and the ADSP-1101 Digital processing. The 27C128 EPROM (lower right) contains the configuration data for the 5 Xilinx XC2000 chips. The many trimpots and jumpers are to configure it for various sensors. Yes, this is a very dense board. What you don't see is that beneath all the 0.6" wide, socketed DIP ICs are many additional 0.3" DIPs.

maxscan1
Closeup of the analog front-end.
maxscan2
Close-up of the ADC and PLL sections. All resistors are hairpin (vertical mounted). Looking forward to the coming of surface mount!
maxscan3

We used Xilinx DOS-based XACT design tool to design the FPGAs. There was no HDL programming then, so we used the physical layout of the chip and simple logic equations for each block to program each logic cell, and then hand routed the interconnects.  We learned to use the long 'global' and fast, local interconnects wisely. Shep and John designed optimized register files, loadable counters, and other logic functions to use the XC2000 architecture efficiently. The hundreds of CMOS switches that provided the interconnect in these FPGAs were called PIPs. Programmable Interconnect Points. We affectionately called this early FPGA design process "PIP Bashing". The tools at the time were inefficient and we could get higher density and speed by hand designing the pinout, placement, logic and routing. We got good at implementing common logic functions using the Xilinx LUT functions. Once we understood the low level functions of the FPGA, we would regularly achieve 90-98% utilization.  Every signal path was checked for timing to ensure timing margins. This was yet-another skill we developed, that is now pretty useless now that high-level HDL compilers and fitters are so efficient. FPGAs of today are too dense and complicated for hand-routing. 

MaxScan and Digicolor Replacements for MV20/200/250: AS, AC, AD Modules

AS and AD replaced the functions of MaxScan with a much smaller and lower cost module. The customer knew which sensor they needed, and so could order AS for analog, AD for digital, and AC for color sensors. Board area for these modules is 5.3 sq in vs 58 sq in for MaxScan.  What a difference 5 years made, 1986 to 199. The VME interface was replaced by the simpler MV20 Internal bus on a Memory SIMM connector. The MaxBus connections were replaced by MV20 crosspoint connections, also on the SIMM connector. The Xilinx XC2000s, bipolar PALs, and SRAM timing generators were replaced by an Actel FPGA and an Altera CPLD. The pixel gain and offset functions could be easily implemented using MV20's image memories and AU's math capability. The shrink was also enabled by double-sided SMT, flex-print connectors, single chip programmable filter, analog multiplier, smaller ADCs and FIFO. Here are the front and rear sides of AS.


asrear asfront

Here is the block diagram for AS:

AS

ROISIMM Image Memory Modules

MaxVideo 20 can have up to 6 ROISIMM Image memories. These are triple ported and ROI capable, 1MB image memories in a SIMM form factor.   Each ROISIMM is a triple-ported Image memory. It can receive one ROI (Region of Interest, see below) and transmit another, while simultaneously being random accessed by the CPU. Each consists of eight 1Mb, 256Kx4 VRAMs (Video RAMs), two ROI timer FPGAs, three Altera CLPDs, and four small PLDs (Programmable Logic Devices). The two 44 pin Actel's are the ROI timers for the transmit and receive ports. The large Altera CPLD is the addressing and bus interface logic, and control registers. The smaller CPLDs and PLDs are the data paths. 

Here are both sides of a ROISIMM.
roisimmFront  roisimmRear
Here is the block diagram for ROISIMM.


roisimm


MaxVideo 200 and 250 used the newer VSIM memories. These replaced the 1MB VRAMs on ROISIMM with 2MB or 8MB SDRAMs, and replaced the 10 programmable logic ICs with a single VSIM ASIC. More, faster, better, cheaper, smaller, lower power, easier to manufacture.... The usual improvements.

Pipelined Image Processing: VFIR example

VFIR-10 was one of the original MaxVideo boards, and one that exhibits the power of pipelined image processing. FIR filtering is used in all kinds of signal processing, but particularly in image processing. FIR filters can perform high-pass, low-pass or edge filtering, simply by changing filter coefficients.  VFIR performs either 3x3 or 10x1 FIR filtering on 8 bit images. The  multiplier coefficients, delay lines lengths, and a few other support functions are all set by the user over the VME bus (using ImageFlow software).  The 1H delay lines present vertically-adjacent values to the filter, allowing 3x3 kernel filtering.

We call these 2D FIR filters Convolvers because they perform mathematical convolution, which can be used as image correlators to enhance small features in an image. These can be applied to a Feature- lister to locate their X-Y locations.

Here is the block diagram of VFIR-10. In hardware reality, it uses five 8x8 multipliers clocked at 20MHz to provide 10 points of filtering at 10MHz. Each multiplier performs 2 multiply-add points at 10MHz. The multipliers are implemented with Analog Devices ADSP-1008 8 bit Multiplier-Accumulators. The digital delay lines are implemented as SRAMs with programmable counters used to set their delay length.

vfir

Here is the block diagram for the Analog Devices ADSP-1008A 8 bit multiplier-accumulator used on VSIM.
adsp1008

ROI Processing

ROI (Region of Interest) processing allows efficient use of memory and processing elements. It allows images, or subsets of images, from very small to very large, to be processed in a single pipeline task. ROI processing in Hardware is fairly challenging. Not only is complex addressing required, but even more complex timing also required. And the challenges are increased when DRAM and SDRAM is used.  Only image Source and Destination boards required ROI timing. Most Pipelined processors just processed the data as it came, with a fixed number of pixels and lines of delay.  But the source and destination timings need to compensate for the pipeline delays of the various processing elements. The 8 bit MaxBus P4 connector was re-configured to implement four, 2 bit (H and V sync) ROI timing busses. One board (or function) would be the ROI Timing transmitters, and other source or destination boards in the pipeline would be ROI timing receivers.

This diagram shows the controls (via registers) used in by ROI controller.  Memory start address and address pitch (address increment for second and subsequent lines) are controlled by the memory controller. This is a straightforward process with static RAM, but fairly complex with burst DRAM modules such as ROIStore, Megastore, ROISIMM, and VSIM.

roitiming

An example of a simple ROI pipeline would be a single image store sending an 800 x 600 image, an 8x8 Convolver processing the image, and another image store receiving the processed result. The source image store would typically transmit its ROI timing at 800 pixels and 600 lines. The 8x8 Convolver might have 12 pixels of H delay, and 8 lines of V delay. The receiving frame store would be set up to receive the data 12 pixels and 8 lines later.

1996 IBM Satellite Image System

IBM military division in Gaithersburg MD was interested in a new satellite image system. For them, Datacube developed a third generation exploitation system. This powerful system used an extremely high bandwidth image memory and an Address generator by Erich Whitney, capable of 7x7 spatial transformation matrices, calculated with double precision floats. A powerful new display system, XI was developed to display the results.

Unfortunately, due to the lack of a firm contract, IBM took only a couple of these systems and one department-year of Datacube's talented engineering efforts were effectively wasted. But Datacube had other projects going. It leveraged several key technologies with MaxVideo 20. An off-the-shelf disk storage system was integrated to be used for medical and image exploitation systems, but this system had unsolvable technical problems, so Shep developed MD, based on an off-the-shelf external SCSI RAID box. A 12 bit, 20MHz digitizer, Digi-12 was developed by Dave and was a key element in the Picker Digital Radiology system. Datacube designed an interface to a Sky array processor to obtain a GE military contract for a submarine sonar system.
 

List of Hardware Products

prod1

prod2

Product Information

Datacube Product Presentation Video (10min, low res video, but quite informative.)

Here are the latest printed (up until 1999) VME product data sheets. Most earlier (80s and early 90's) VME MaxVideo boards are not listed.

Here are the 1999 PCI product data sheets:
PSMODs: Processing and Storage MODules for MaxPCI
 Software Products
 Datacube System Products

MaxPCI Family Products Presentation

PCI Industrial Workstations

Datacube PCI WIT Graphical Programming Software Presentation

Application Notes

Corporate Stuff

Vertical Integration Groups

Datacube recognized the need to better help its customers develop complex solutions in the medical, web inspection and machine vision markets. So three vertical market integration development groups were formed. Shep headed Medical Imaging, Dave Simmons headed Web Inspection, and Scott Roth headed Machine Vision. Each of these groups developed systems for OEMs in their respective markets: Bobst and Crane Paper in web, Picker and Varian in Medical imaging, and many customers in Machine Vision.

Critical Groups

No company is solely engineering, and Datacube could not have existed without dedicated teams in all of these areas:

What happened to Datacube?

Datacube was always a hardware-centric company. Its products competed against software solutions running on CPUs. When CPUs were in the 10-1000MIPS range, Datacube's 1G-10G solutions were very appealing. When CPUs and multi-core CPUs began to exceed 1000MIPS and then multi-core GPUs became readily available, Datacube solutions were no longer needed except for the very highest-end applications. Frame grabbers became USB sticks. Real-time video disks are now just disks. Laptops can do a fair amount of real-time video tricks. A single FPGA has hundreds of high-speed multipliers, millions of gates, megabytes of internal RAM and practically unlimited external DDR RAM. The gross sales on the few applications that require hardware solutions are not adequate to sustain a business.

Datacube always had the attitude that the best way to protect our IP was to simply stay ahead of the competition. Stan and the leaders also felt that patents were a waste of time and money, that they attracted competition and potential infringement suits. So despite the many amazing inventions, firsts and ideas developed, there were few patents filed. This lack of patents ultimately left no base of technology to licensing opportunities. The IP of hardware-based solutions to Imaging processing

A key medical imaging project for GE Medical was developed by the Datacube Medical group 2-3 years before the competitor, Mercury, could deliver a solution. GE decided to go with Mercury.  This decision hurt Datacube. In the next years, several key people went to Mercury. Mercury has since abandoned all markets except Military. Good.

Others stayed in the imaging market, working for a few small companies. I went to Analogic where I ran engineering for the T&M (Test and Measurement) division for 5 years. I was a bit burned out on imaging, having designed video and imaging systems for 25 years. I also saw that the need for my analog skills in Video were no longer needed, so I moved to instrumentation, T&M and ultimately Medtech.  I since worked for 2 medical companies, one fiber company, and several instrumentation companies. 

In the end, Datacube technology and assets were sold to a company that would sell of the remaining assets for a few years.



From the Datacube Wikipedia page:

Early History

Stan Karandanis, Datacube's President and CEO's early career followed the leaders in the semiconductor field from Bell Labs toTransitron to Fairchild. Stan was director of engineering at Monolithic Memories (MMI) when John Birkner and H.T. Chua designed the first successful programmable logic device, the PAL. Stan's friends and contacts in the semiconductor field were instrumental in providing Datacube with leading-edge components for its dense and powerful products.

Datacube was founded in the mid-70's by Stan and J Dunn. In the early days Datacube manufactured board level products for the Multibus, one of the first computer bussed developed for microprocessors. Early boards designed by J Dunn were PROM, RAM and character generator boards. Of these, character display boards such as the VT103 and VR107 were the best sellers and were used in Prom programmers and similar systems.

An OEM asked if a frame grabber could be built on a Multibus board and J Dunn rose to the challenge. At the time, frame grabbers were large boxes with multiple boards. The VG120 was the first ever commercial, single board frame grabber: based on PALs, it had 320 x 240 x 6 bit resolution, grayscale video input and output. Stan then hired Rashid Beg and Robert Wang from Matrox to develop the first Q-Bus (DEC LSI-11) frame grabber. They developed the QVG/QAF120 dual board, 8 bit product primarily for a new machine vision startup, Cognex. Unfortunately while they were developing it for Datacube, they were apparently planning to spin off and form a competitor, Imaging Technology. To recover from this loss and to complete the QVG120 product, Dave Erickson was hired as a consultant in 1981 from Octek by then engineering manager Paul Bloom. He came on full time in 1982 as did Dave Simmons who was to head applications, and Bob Berger who was to head software. At this time Imaging Technology Inc. (ITI) was developing a line of frame grabbers for Multibus and Q-bus with a 'real time' image processor based on a single point multiplier, adder and look-up-table (LUT). In 1983, Stan hired an ex-co-worker of Bob Berger's, Shep Siegel from Ampex who had worked on the advanced and successful Ampex Digital Optics (ADO) real-time video spatial manipulator for the broadcast TV market.

With J's help, Dave developed the VG123 Multibus and Q-bus high resolution frame grabbers. During this development Paul Bloom was killed in what was apparently a gangland style murder. The mystery of why this happened was never solved. Dave Erickson was promoted to engineering manager to replace Paul. Shep came on in to add the SP123 image processor to the '123 family. But having worked on ADO, saw the limitations of the single-point architecture and had a vision of what could be done by applying pipelined real-time imaging. He came with an understanding of DSP, image processing, filtering, and 2D warping, and with programmable logic in hand saw what could be done. Dave and J now had developed a handful of single board frame grabbers deployed on most standard busses, Each potential new customer required one or two features not currently available. And designing, laying out (using hand taped artwork) and manufacturing a board for a single customer was risky, slow and expensive. What was needed was a way to leverage the technology developed so that it could be applied to a wider customer base. Dave felt that a modular architecture where functions could be easily added and a system tailored to a customers needs was critical. At this time the VME bus was being introduced by Motorola for their 68000 processors. The automotive and military markets liked VME because it was open and rugged. Dave, Shep, Stan, Bill Southworth and others embarked on a marketing road trip to visit potential customers in medical, automotive and military markets to inquire what imaging functions they required.

MaxVideo 10

A Modular and expandable system based on the VME form factor could meet many customer needs. MaxVideo and the MaxBus were born. The market research done showed the primary functions required as well as a road map for the next few years. The first seven MaxVideo boards were Digimax (digitizer and display), Framestore (triple 512^2 image memory with unprecedented density), VFIR (first real-time 3x3 image filter, SNAP (3x3 Systolic Neighborhood Array Processor), Featuremax (real-time statistics) SP (single point general purpose processor) and Protomax (MaxVideo prototyping board). 10 beta customers were lined up to receive the first 7 boards. MaxWare was the software and drivers written to control the new boards.

The first demo of the new hardware consisted of a camera's output being processed in real time by VFIR and displayed on a monitor. Shep wrote a loop that varied the VFIR coefficients on a frame-by-frame basis to demonstrate not only the the real time functionality, bu that it  could be easily changed.  In the spring of '85 The product was not production-ready so private viewings were set up with potential customers at the Detroit Vision'85 show. Customers were blown away. Three months later, the first shipments went out.

MaxBus was based on the '123's expansion bus. It required accurate synchronization: clocking and timing of each board plus a flexible way to route data from function to function.  A simple differential ECL bus with a driver on one end and terminator on the opposite end was used. For data, 14 pin ribbon cables allowed 8 bit 10MHz data to be routed from any output to any input.

At this time the company started to grow. Barry Egan was brought on to head manufacturing, entrepreneur Barry Ungar was brought on as President. Bob Berger expanded the software department and moved the main computers from CPM machines to Unix machines based on DEC's LSI-11s. A Unix based Pyramid mainframe computer was purchased for hardware and software development. Bob bought the first Sun workstations and set up the first ethernet. He registered datacube.com as the 68th internet URL ever. In hardware, John Bloomfield was hired from Ampex per Shep's recommendation.

The second tier of MaxVideo products was developed. Shep began the first image warper consisting of Addgen, Interp, and XFS. John Bloomfield expanded the fixed 512x512 processing to include Regions-of-interest (ROI) processing. He began developing with the new FPGAs from Xilinx. RoiStore, MaxScan (first arbitrary sensor interface), VFIR-II and MaxSigma. These products firmly established Datacube as the technology leader in real-time imaging.

By now MaxWare with its low level control was running out of steam. It was clear that a better way for software to manage the complex new imaging pipelines was needed. ImageFlow was developed. it provided full pipeline delay management and optimization, and a consistent API for programming imaging hardware. Key software people were brought on: Ken woodland, Stephen Watkins and Ari Berman.

Recognizing that not every imaging function could be best done in a pipeline, Shep teamed with Analog Devices new DSP group to develop Euclid, a general purpose DSP, based on the brand-new ADSP2100. Analog Devices signed up Datacube as a Beta-site for the device. Datacube contracted with a compiler designer, Preston Gurd from U-Waterloo to develop the first C compiler for the ADSP2100.

Color digitization and display was required for some markets, so Shep teamed with a broadcast TV EE consultant Robert Bleidt to develop Digicolor. In addition to performing many color-space conversions, it also had a Time-base corrector for added sync stability.

Datacube's first generation image Warper caught the attention of the 'image exploitation' industry and in particular, Lockheed. Shep developed the second generation warper for ROIs: Addgen MkII and Interp MkII. John developed Megastore 8/32 to handle the large images that this market required. By now the original SP and Featuremax were running out of steam so SP MKII and FeaturemaxMkII were developed. Dave developed the first Datacube ASIC: MaxMux for RoiStore, and as its own flexible switch board.

To address the need to combine imaging and workstation graphics, John and Dave developed MaxView, a high resolution display with the ability to perform real time image display in a window. Steve ported X-windows to this display. Despite the fact that a single box of MaxVideo hardware could replace a room full of hardware at Lockheed, the product was not bought. Lockheed made too much money on the legacy system to want to update to the newer, smaller, better system. Your tax dollars at work.

A typical system now consisted of a MaxBox 20 slot VME chassis with up to 20 boards installed. The largest MaxVideo system ever built was by Honeywell for aerial target identification. It consisted of five 20 slot chassis full of MaxVideo Hardware. A new MaxBus repeater was developed for these very large systems. Another important military design-in for MaxVideo 10 was Martin Marietta's FLIR pod test system. Sandia National Labs adopted MaxVideo for a Radar image targeting system.

MaxVideo 20

The next step was to implement up to a full rack of MaxVideo 10 hardware in a dual slot VME package, increase the pipeline to 20MHz, maintain the modularity and flexibility, and eliminate most of the blue MaxBus cables. MaxVideo 20 was born. This required a new 3-port image memory module base on the 72 pin SIM form factor and developed by J Dunn. Up to 6 memories were used on each Max20. Max20 also leveraged a new line of Imaging chips from LSI logic, including a 32x32x2b digital crosspoint and an 8x8 20MHz FIR filter. J developed a new display controller, AG capable of up to 40MHz display, and Dave developed a new family of 20MHz analog and flexible digital front ends, AS and AD. J developed a color digitizer, AC. A real jewel in MaxVideo20 was the new general processing ASIC, AU developed by John. This device contained many innovative linear, nonlinear and statistical imaging functions. It's architecture was to be the core of not only Max20 but the next generation imaging system as well.

The memory SIM was implemented with CPLDs, FPGAs and Graphics DRAM. It was limited to 1MB of memory and required 14 devices tightly packed onto the SIMM. Shep developed VSIM, a fast and powerful ASIC to control high density SDRAMS and built a 3 device replacement SIMM. It was a triple ported image memory capable of 1, 4 or 16MB memory sizes, up to 40MB/s input and output bandwidths, and contained numerous image processing functions as well. VSIM technology would be the core image memory technology to be used on numerous future products.

A number of MaxModule processing modules were developed for MaxVideo 20. One of these was Shep's MiniWarper, a 20MHz real-time warper based on a new ASIC design, MW4242. With the advent of MaxModules, it was now possible to implement an imaging function on a small and simple board with much less overhead than a full VME board.
MaxVideo

Technologies

Stan's Rolodex contained leaders in the semiconductor market. Combined with Datacube's willingness to take risks on promising new technologies, this gave Datacube a strong competitive edge in applying new technologies. In the early days, Video DACs were large modules or expensive and power hungry bipolar devices. Datacube worked with Silicon Valley startup Telmos to develop the first integrated Video DAC. This was used on the '128 family as well as Digimax. It was the starting point for all Video DACs and RAMDACs by Brooktree and others. Datacube was to ride several technological waves including fast ADCs, disc drives, DRAM, DSP devices and custom ASICs. 

But programmable logic was the key to Datacube's functional density. From the early days of bipolar PALs and PROMS to GALs, to every generation of CPLDs from Altera, and FPGAs from Xilinx and then Actel and Quick Logic. Many semiconductor manufacturers acknowledged that Datacube could help bring their new products to market. Datacube was an ideal beta site and they shared their roadmaps, latest offerings, and support. Best of all Datacube contributed new product ideas that these companies then developed.

ASICs were also critical to Datacube's success. From the first small crosspoint, MaxMux: 3000 gates in 2 micron, AU: 40,000 gates in 0.8u, through VSIM, MiniWarper, AU40 and IXP. Each of these devices were leveraged across several products. After IXP the density and cost of FPGAs began to catch up to full ASICs and so FPGAs became the technologies of choice.

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Last updated 12/20/202