Acquisition - MaxACQ Family

• Common MaxACQ timing and FIFO circuitry (QZ) located on motherboard allowing user to select from a family of interchangeable acquisition modalities

• Up to 80 Megabytes per second of acquisition bandwidth

  • 300K pixel FIFO allows seamless continuous V acquisition
  • flexible pixel, H and V timing synchronization includes external, PLL generated and internal master generated modes

• Acquisition modality-specific circuitry on a screw-down daughter card allows user configuration from a wide family of modules.

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